ISMP 2024

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Abstract

• The rapid evolution of advanced packaging technologies, including hybrid bonding, presents significant challenges for metrology, defect inspection and physical failure analysis (PFA). To address these challenges, innovation in microscopy techniques and related workflows are required. The development of next-generation analytical tools that can tackle technologies for heterogeneous integration of ICs and chiplet architectures is a challenge to engineers at universities, research institutes and equipment manufacturers. With respect to nondestructive imaging, a balance between acquisition speed and achievable resolution is always a consideration for engineers [1]. Scanning acoustic microscopy (SAM) continues to be the tool of choice for inspecting interfacial integrity (e.g. delamination), and detecting defects (e.g. voids, cracks) in bonded wafers [2]. However, conventional SAM techniques reach limits for 3D-stacked dies since highly penetrating low frequency acoustic waves are unable to provide high resolution imaging of high-density submicron interconnects, and because of requirements to spatial resolution of 500 nm and below. In addition, the convolution of signals from various die interfaces makes it difficult to select the correct signal for rendering the right image from the interface of interest. Several beyond state-of-the-art approaches are addressing these challenges. We will demonstrate the detection of voids in through-silicon-vias (TSVs) applying the new GHz-SAM technology [3]. SAM interferometry, where the defocused sound field induces surface-acoustic-waves, provides unique interference patterns associated with the quality of each TSV. Finally, a fully automated high-efficient End-to-End Convolutional Neural Network model classifies thousands of TSVs and provides statistical information [4]. X-ray microscopy and high-resolution X-ray computed tomography (XCT) are well-known FA techniques that have been applied to visualize defects in metal interconnects and package structures such as TSVs, Copper pillars and solder microbumps [5,6]. However, usually a compromise had to be made between image quality and scan throughput, and state-or-the-art laboratory nano-XCT requires a destructive workflow. High-resolution imaging of voids in Cu-TSVs and AgSn microbumps will be shown, using conventional nano-XCT after thinning the Si down to about 50 m. To image defects with sub-500nm and sub-100nm size, respectively, further development of micro-XCT and nano-XCT techniques are needed. To ensure a highly reliable inspection method, the time for image acquisition must be reduced significantly without sacrificing the resolution of the X-ray images. Ways for a drastic throughput increase are high-brilliance laboratory X-ray sources and the application of AI algorithms for imaging of objects with large form factors (dies, wafers) and high-speed data processing. In addition, we will demonstrate for solid–liquid interdiffusion (SLID) bonded Cu/Cu6Sn5/Cu interconnects that in the hard X-ray regime, i.e. at photon energies > 10 keV, destructive sample preparation steps for nano-XCT are not needed [7]. An outlook for a seamless workflow for advanced package FA and defect inspection, that combines acoustic and X-ray techniques to auto-detect and auto-classify defects, with the goal to improve throughput and defect detectability, will be presented.
  
  [1] EDFAS Electronic Device Failure Analysis Technology Roadmap, ASM International (2023)
  [2] S. Brand et al., Microsystem Technologies 21, 1385–1394 (2015)
  [3] A. Phommahaxay et al., Proc. 63rd IEEE ECTC 2013, Las Vegas/NV, pp. 227 - 231 (2013)
  [4] P. Paulachan et al., Scientific Reports 13, 9376 (2023)
  [5] Y. Sylvester et al., Proc. ASMC, Saratoga Springs/NY, pp. 249–255 (2013)
  [6] E. Zschech et al., Proc. 20th PanPacific Microelectronics Symposium, Kolao/HI (2015)
  [7] B. Lechowski et al., Nanomaterials 14, 233 (2024)

Biography

• Ehrenfried Zschech is a consultant with hands-on experience in the fields of advanced materials, nanotechnology and microelectronics as well as process control and quality assessment. He holds honorary professorships for Nanomaterials at Brandenburg University of Technology Cottbus-Senftenberg and for Nanoanalysis at Dresden University of Technology. His activities include high-resolution X-ray imaging and the development of customized solutions for a broad range of applications including package failure analysis, metrology and inspection in microelectronics. Ehrenfried Zschech received his Dr. rer. nat. degree from Dresden University of Technology. He had several management positions at Airbus, at Advanced Micro Devices, at Fraunhofer and at the start-up deepXscan. Ehrenfried Zschech is Member of the European Academy of Science (EurASc) and Member of the of the German National Academy of Science and Engineering (ACATECH). In 2019, he was awarded with the FEMS European Materials Gold Medal.

Abstract

• The semiconductor packaging industry is expected to grow in the coming years, driven by the increasing demands for semiconductor chips in various applications, such as smartphones, autonomous vehicles, 5/6G, high-performance computing, IoT devices, and artificial intelligence. Another trend is the increasing adoption of heterogeneous integration, where different types of chips, such as CPUs, GPUs, and memory, are integrated into a single package to improve performance and reduce power consumption.
  To overcome the limitations of performance/power/density/bandwidth of cutting-edge systems, and to create new business opportunity and new values, the importance of advanced packaging technologies is more increased. For the above reasons, the future of the semiconductor packaging industry looks promising, with the increasing demand for semiconductor chips in various applications and the emergence of new packaging technologies driving growth and innovation in the semiconductor industry. Major semiconductor players accelerate the competition to lead semiconductor industry hegemony by the evolution of advanced packaging technology such as chiplets and 2.5D/3D heterogeneous integration.
  SK hynix drive the innovation of packaging technology to meet the demand for higher bandwidth and capacity of memory devices requiring in the increased AI workload applications such as the advent of ChatGPT, an artificial intelligence chatbot. High Bandwidth Memory (HBM), offers the largest capacity and bandwidth and also comes with the most improved power efficiency enabled by an advanced packaging technology of novel 3D chip stacking. SK Hynix is taking the lead in the HBM market. It developed the world’s first HBM in cooperation with AMD in 2013 and continuously released every-generation HBMs (HBM2/HBM2E/HBM3/HBM3E) for the first time in the industry and has secured a market share of 60-70 percent.
  The chip-let packaging technology based on heterogeneous integration will be another key driver for memory-centric systems various combination of logic and memory devices.
  By the evolution of advanced packaging technologies, SK Hynix will continuously lead the competitiveness of memory business and prepare the business innovation for beyond memory era.

Biography

• Dr. Lee has been one of critical leaders who are leading the era of 3D TSV stack memory such as HBM (High Bandwidth Memory) in semiconductor industry. He has contributed broadly to, and led teams in, 3D integration/packaging R&D including core technology/product development/reliability study and mass production for HBM over 27 years. Dr. Lee received the Ph.D. degree in machine intelligence and systems engineering from Tohoku University, Japan, in 2000. During his doctoral research at Tohoku University.