ISMP 2024

Abstract

• Technologies for heterogeneous integration of ICs and chiplet architectures face significant challenges to ensure the requested mechanical robustness of microelectronic products, particularly for use cases that require lifetimes much longer than in the past and for safety-critical applications. Microcracks in backend-of-line stacks, introduced e.g. during dicing of the wafer, are serious reliability concerns since they can grow and ultimately cause catastrophic failures in chiplets. Advanced packaging technologies and the integration of materials with different coefficients of thermal expansion (CTE) cause thermomechanical stress in packaged systems and in each chiplet, both during manufacturing and during operation of microelectronic products, that accelerates degradation processes such as microcrack propagation in backend-of-line stacks.
  For the understanding of reliability-limiting degradation and failure mechanisms in 3D-stacked ICs and for package failure analysis, new analytical techniques are needed. In this talk, the inherent advantages of high-resolution transmission X-ray microscopy (TXM) and nano X-ray computed tomography (XCT) for the nondestructive imaging of kinetic processes such as microcracks evolution in chiplets is demonstrated – as opposed to destructive failure analysis methods. We will show how the combination of a micromechanical test and high-resolution X-ray imaging allows to perform in-situ studies of crack propagation in backend-of-line stacks. A miniaturized Double Cantilever Beam (micro-DCB) test was designed and built, to grow microcracks in on-chip interconnect structures by applying a precisely controlled mechanical load and by monitoring force and displacements in the materials at the micro- and nanoscale. The methodology described allows a controlled steering of microcracks, e.g. generated during the wafer dicing process, into regions with relatively high fracture toughness. Based on nano-XCT studies, the effectiveness of guard rings, i.e. metallic structures at the rim of the chiplets, to stop microcracks was shown and input for the design of guard ring structures could be provided.
  
  Keywords: X-ray microscopy, failure mechanisms, microchip robustness, interconnect reliability, crack propagation

Biography

• Dr. rer. nat. Kristina Kutukova, received PhD from the Brandenburg University of Technology Cottbus-Senftenberg, Germany, in 2023. Her doctoral work, focusing on an "In-situ study of crack propagation in patterned structures of microchips using X-ray microscopy" earned her the DGM Young Scientist Award in 2023. Kristina Kutukova was a research associate in the Department of Microelectronic Materials and Nano-scale Analysis at Fraunhofer Institute for Ceramic Technologies and Systems Dresden, Germany, for more than 5 years. In the previous two years, she was acting as Head of the Development and Application Lab at deepXscan GmbH, a start-up company in Dresden, with the main tasks to the develop customized solutions for high-resolution 3D imaging and to coordinate development projects. Since June 2024 she works at Fraunhofer Institute for Reliability and Microintegration, All Silicon System Integration Dresden as a Scientific Advisor.

Abstract

• The rapid evolution of advanced packaging technologies, including hybrid bonding, presents significant challenges for metrology, defect inspection and physical failure analysis (PFA). To address these challenges, innovation in microscopy techniques and related workflows are required. The development of next-generation analytical tools that can tackle technologies for heterogeneous integration of ICs and chiplet architectures is a challenge to engineers at universities, research institutes and equipment manufacturers. With respect to nondestructive imaging, a balance between acquisition speed and achievable resolution is always a consideration for engineers [1]. Scanning acoustic microscopy (SAM) continues to be the tool of choice for inspecting interfacial integrity (e.g. delamination), and detecting defects (e.g. voids, cracks) in bonded wafers [2]. However, conventional SAM techniques reach limits for 3D-stacked dies since highly penetrating low frequency acoustic waves are unable to provide high resolution imaging of high-density submicron interconnects, and because of requirements to spatial resolution of 500 nm and below. In addition, the convolution of signals from various die interfaces makes it difficult to select the correct signal for rendering the right image from the interface of interest. Several beyond state-of-the-art approaches are addressing these challenges. We will demonstrate the detection of voids in through-silicon-vias (TSVs) applying the new GHz-SAM technology [3]. SAM interferometry, where the defocused sound field induces surface-acoustic-waves, provides unique interference patterns associated with the quality of each TSV. Finally, a fully automated high-efficient End-to-End Convolutional Neural Network model classifies thousands of TSVs and provides statistical information [4]. X-ray microscopy and high-resolution X-ray computed tomography (XCT) are well-known FA techniques that have been applied to visualize defects in metal interconnects and package structures such as TSVs, Copper pillars and solder microbumps [5,6]. However, usually a compromise had to be made between image quality and scan throughput, and state-or-the-art laboratory nano-XCT requires a destructive workflow. High-resolution imaging of voids in Cu-TSVs and AgSn microbumps will be shown, using conventional nano-XCT after thinning the Si down to about 50 m. To image defects with sub-500nm and sub-100nm size, respectively, further development of micro-XCT and nano-XCT techniques are needed. To ensure a highly reliable inspection method, the time for image acquisition must be reduced significantly without sacrificing the resolution of the X-ray images. Ways for a drastic throughput increase are high-brilliance laboratory X-ray sources and the application of AI algorithms for imaging of objects with large form factors (dies, wafers) and high-speed data processing. In addition, we will demonstrate for solid–liquid interdiffusion (SLID) bonded Cu/Cu6Sn5/Cu interconnects that in the hard X-ray regime, i.e. at photon energies > 10 keV, destructive sample preparation steps for nano-XCT are not needed [7]. An outlook for a seamless workflow for advanced package FA and defect inspection, that combines acoustic and X-ray techniques to auto-detect and auto-classify defects, with the goal to improve throughput and defect detectability, will be presented.
  
  [1] EDFAS Electronic Device Failure Analysis Technology Roadmap, ASM International (2023)
  [2] S. Brand et al., Microsystem Technologies 21, 1385–1394 (2015)
  [3] A. Phommahaxay et al., Proc. 63rd IEEE ECTC 2013, Las Vegas/NV, pp. 227 - 231 (2013)
  [4] P. Paulachan et al., Scientific Reports 13, 9376 (2023)
  [5] Y. Sylvester et al., Proc. ASMC, Saratoga Springs/NY, pp. 249–255 (2013)
  [6] E. Zschech et al., Proc. 20th PanPacific Microelectronics Symposium, Kolao/HI (2015)
  [7] B. Lechowski et al., Nanomaterials 14, 233 (2024)

Biography

• Ehrenfried Zschech is a consultant with hands-on experience in the fields of advanced materials, nanotechnology and microelectronics as well as process control and quality assessment. He holds honorary professorships for Nanomaterials at Brandenburg University of Technology Cottbus-Senftenberg and for Nanoanalysis at Dresden University of Technology. His activities include high-resolution X-ray imaging and the development of customized solutions for a broad range of applications including package failure analysis, metrology and inspection in microelectronics. Ehrenfried Zschech received his Dr. rer. nat. degree from Dresden University of Technology. He had several management positions at Airbus, at Advanced Micro Devices, at Fraunhofer and at the start-up deepXscan. Ehrenfried Zschech is Member of the European Academy of Science (EurASc) and Member of the of the German National Academy of Science and Engineering (ACATECH). In 2019, he was awarded with the FEMS European Materials Gold Medal.

Abstract

• Semiconductors require a wide variety of interconnection methods ranging from a few millimeters to a few micrometers in size, for example. Materials and process parameters must fit to the requirement in each case. For high performance computing (HPC), with the increase in system integration, Si dies have become denser and larger resulting in manufacturing costs skyrocketing. Since lithography limit coming, chiplet technology in the back-end process has become a key technology supporting the new generation of HPC, in which ultra fine and dense interconnections are needed. Although chiplet technology has already begun, it has not reached the standard level. On the other hand, power semiconductors have stepped into a new era, wide band gap, such as SiC and GaN. These WBG semiconductors can reduce substantial energy loss happening in Si power semiconductor. Bonding technology is again to be explored to support these WBG’s benefits such as high temperature operation and high current density. Both for HPC packaging and for WBG packaging, solder less bonding technology are opening new field such as Cu-Cu direct bonding and Ag sinter joining. After these bonding technologies are mentioned first, remaining issues in these technologies will be briefly summarized.
  Many major automotive related companies have already made announcement of their own roadmap of applying advanced semiconductors especially for AI technology and sensing for autonomous driving, for which semiconductors are, for example, sensors and ADAS CPUs. The Si lithography node rule will reach less than 4 nm for vehicles even in near future. These semiconductors inevitably require multi functions composed of multichip structure. No one has discussed on the chiplet technology for automotive applications, which requires high and very severe level of reliability.
  Substrate is one of the essential components for advanced semiconductors. The built-up layer formation technology, vertical interconnection, is indispensable for substrates essential for cutting-edge applications. Micro-via interconnection that connects the upper and lower interconnections of the built-up layers has been serious failures in the market due to miss understanding of quality of via bottom bonding. Nano voids formation in the via bottom increases the weakness of substrates.
  
  Some of the current activity in F3D laboratory mentioned above will be introduced in the presentation.
• 
  Fig.1 Electrification of vehicles

Biography

• He received the degree of Dr. Engineer from Tohoku University in 1982. He became a research assistant of ISIR (Institute of Scientific and Industrial Research), Osaka University in 1982, an associate professor of National Defense Academy in 1986, and a professor of ISIR of Osaka University in 1996. He was the director of Nanotechnology Center of ISIR in 2007-2009, the director of ISIR in 2018-2020. He is currently Specially Appointed Professor and Professor Emeritus of Osaka University, Executive Advisor of Daicel Corp., and the Head of 3D Packaging Technology Division of Leading-edge Semiconductor Technology Center (LSTC).

Abstract

• The AI era has arrived and to enable and perpetuate it, the semiconductor advanced packaging (AP) industry needs to innovate in a torrid pace to keep in tandem the exponential growth of the Gen AI computing power.
  Rising to the challenge, ASMPT has been leveraging its first mover market position in advanced packaging to continue innovating its end-to-end solutions to scale with the latest packaging architecture with the most demanding chiplet interconnects and heterogeneous integration formats.
  Going forward, the AP industry shall undergo a “Power of N” transformation where interconnect pitch shall shrink rapidly along with thinner and bigger package formats, demanding new technologies in materials, process and equipment signaling a need for a complete and robust ecosystem to evolve for Gen AI to continue scaling.

Biography

• Mr. Lim Choon Khoon is a Senior Vice President of the Group, Co-CEO of the Semiconductor Solutions Segment, and CEO of the Segment’s Advanced Packaging Business Group.
  
  He holds a Bachelor of Science (Honours) in Production Engineering and Production Management from the University of Nottingham, UK. Mr. Lim’s career included key engineering, manufacturing, and regional functional and global general management roles with several global semiconductor companies. Since July 2006, Mr Lim’s responsibilities in the Segment included equipment product marketing and sales, key account management and leading the Segment’s advanced packaging initiatives. He currently leads the Segment’s Advanced Packaging Business Group, which provides the industry’s leading first-level interconnect technologies and end-to-end solutions for advanced packaging. These solutions are well positioned to serve and scale with the most demanding advanced packaging needs.

Abstract

• The recent surge in demand for AI has led to an explosive increase in the need for high-performance computing and advanced packaging technologies. Although the current focus is on data center applications, it is expected that the demand for AI functionalities will also spread into consumer electronics, such as smartphones, refrigerators, robot vacuums, and more. However, current AI semiconductor and packaging technologies are not yet at a level where they can be directly applied to consumer electronics, due to challenges related to form factor, cost, reliability, and heat dissipation, which will require significant modifications. Additionally, due to the difference in integration density between AI semiconductors and conventional semiconductor components used in consumer electronics, there is a need to develop new heterogeneous integration technologies at the board level. In this talk, I will discuss the challenges that must be addressed and the necessary technologies for the broader adoption of advanced packaging in consumer electronics.

Biography

• Jichul Kim received his PhD in Mechanical Engineering from the University of California, Los Angeles, in 2009. Dr. Kim is currently serving as a Master (VP of Technology) at Samsung Electronics, where he specializes in semiconductor packaging and printed circuit board assembly technologies for consumer electronics. During his tenure in Samsung’s Mobile Division, Dr. Kim led efforts to reduce semiconductor package form factors and achieve system-level high-density integration for Samsung’s Galaxy devices. Since 2023, Dr. Kim has been with Samsung Electronics’ Digital Appliance Division, where he is establishing AI platforms for next-generation, hyper-connected AI home appliances.

Abstract

• The business landscape is experiencing great change with the continued rise of technology companies that are driving social media, cloud computing, search, online commerce, and big data, leading to integrated hardware-software driven applications and unprecedented growth of application spaces. These needs have been accomplished by advanced node of silicon wafer fabrication. However, this track encounters the dead-end by physical and economic reasons. It is well known that die costs continue to increase at advanced node from 7nm or beyond and the momentum for the silicon node scaling is lost.
  One of the prime candidates of breakthrough is Heterogeneous Integration. By the definition of the Heterogeneous Integration in HIR Roadmap, it is referred to “the integration of separately manufactured components into a higher-level assembly (System in Package – SiP) that, in the aggregate, provides enhanced functionality and improved operating characteristics”.
  Heterogeneous Integration will be the key technology direction going forward for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law Scaling into the distant future. Packaging – from system packaging to device packaging – will form the vanguard to this enormous advance. The variety of package types include 2.5D Packages, Fanout/Fan-in Package, Co-Packaged Optics, and Hybrid boded die packages. Also, technology specifics that enable these include Interposers with silicon, glass, or organic materials, high density substrates, and hybrid bonding technologies.
  Heterogeneously integration packages and their assemblies, however, face significant hurdles. The challenges range from managing stresses and handling warpages for fabrication and assembly. As an example, packages for high performance computing become larger in dimension, as large as 100x100mm. Typical subcomponents of a most recent advanced package include a high-density substrate, an interposer, HBMs, logic die(s), and a stiffener. The highly complex structure, assembly process, and multiple material sets cause many new manufacturing problems and reliability issues.
  This presentation discusses thermos-mechanical reliability and manufacturing related challenges for Heterogeneously Integrated Packages and their assemblies.
  
  Keywords: Heterogeneously Integrated Packages, Reliability, Assembly, Warpage

Biography

• Prof. Seungbae (SB) Park is a Distinguished Professor of Mechanical engineering of the State University of New York at Binghamton. He is the director of Integrated Electronics Engineering Center (IEEC), a New York State Center for Advanced Technology (CAT) for electronic packaging.
  
  He has more than 200 technical publications and holds 4 US patents. Dr. Park was elected as an IEEE Fellow, ASME Fellow, Chair of IEEE Electronic Packaging Society Thermal/Mechanical Technical Committee, Chair of ASME Electronics and Photonics Packaging Division.

Abstract

• The rapid growth of information technology has driven an unprecedented demand for computing power, memory, and interconnect bandwidth, coinciding with a slowdown in traditional semiconductor technology scaling. The main bottleneck to overcome in high-performance computing era is the resistance-capacitance (RC) delay and reliability challenges derived from interconnections in chip-level and system-level, respectively. First, in the chip-level interconnect of metal 1 (M1), the effective resistivity of Cu interconnects has increased rapidly due to the reduction of the linewidth of interconnects along with the scaling of the device transistor. Ruthenium (Ru) is often cited as a candidate for the next-generation interconnect metal since Ru is expected to have minimized influence of interface/surface scattering and grain boundary scattering. However, the high melting temperature (T_m), high surface energy and hexagonal close-packed (HCP) crystal structure of Ru results in different process and reliability concerns compared to Cu. Therefore, it is crucial to discuss the potential reliability concerns of Ru interconnects to enable advanced chip-level interconnects. Meanwhile, in the system level interconnections, redistribution layers (RDLs) have been introduced to accommodate a larger number of I/Os and enable further miniaturization. However, as RDL becomes increasingly fine-pitched, the interlayer dielectric spacing between RDLs decreases rapidly, resulting in an increased effective electric field and raising concerns about reliability issues. Notably, since the dielectric in RDL is organic dielectric, it is expected to be more vulnerable to various reliability concerns including humidity and dielectric breakdown. In this talk, potential reliability challenges will be discussed in terms of chip-level interconnect and system-level interconnect, focused on the application of new materials.
  
  Keywords: Reliability challenges, Ruthenium (Ru) interconnect, redistribution layer (RDL)

Biography

• Young-Chang Joo is a professor in the Department of Materials Science and Engineering at Seoul National University in South Korea. He received his BS and MS degrees from Seoul National University and his PhD from the Massachusetts Institute of Technology (MIT) in 1995. He then joined the Max-Planck Institute for Metals Research in Stuttgart, Germany, in 1995, and Advanced Micro Devices, Inc. (AMD) in California, USA, in 1997. He has been a professor in the Department of Materials Science and Engineering at Seoul National University since 1999. From 2020 to 2022, he served as the President of the Advanced Institute of Convergence Technology, an interdisciplinary research institute focused on regional scientific and technological issues. Recently, he served as the Vice Minister for Science, Technology, and Innovation at the Korean Ministry of Science and ICT, which is responsible for strategies for science and technology innovation.
  Young-Chang served on the Board of Directors of the Materials Research Society (MRS) from 2016 to 2018. He received the Haedong Award from the Korean Electronic Packaging Society in 2010 and the LS Nikko Award from the Korean Institute of Metals and Materials in 2016. He is also a member of the National Academy of Engineering of Korea.
  Young-Chang’s research interests range from the fundamental understanding of the mechanical behavior, atomic migration, and structure of nanomaterials to applicable studies on the reliability and degradation mechanisms of devices and systems, including advanced interconnects and packaging for integrated circuits. He has authored over 350 refereed scientific papers and patents.